A content addressable memory (CAM) device is a storage device that is commonly used for high speed search operations because it can be instructed to compare a search key (e.g., a specific pattern of comparand data) with multiple data stored in an associated CAM array. A CAM array typically includes a plurality of rows of CAM cells, each of which can be accessed by a corresponding address for read and write operations. Binary CAM cells, which can store two states of information (e.g., a logic 1 and a logic 0), typically include a random access memory cell that stores data and includes a compare circuit that compares the stored data with a search key to generate a match result. During compare operations, the match results of the CAM rows are provided to a priority encoder via a plurality of corresponding match lines. In response to the match results, the priority encoder determines which matching CAM row has the highest priority associated with it, and outputs the index (e.g., address) of the highest priority match (HPM).
FIG. 1 illustrates a typical binary CAM cell. The CAM cell 100 includes a memory cell 110 and a compare circuit 120. In the example shown, the memory cell 110 is a static random access memory (SRAM) cell including a latch formed by cross-coupled inverters 112 and 114 and including access transistors 116 and 118. The latch stores a single bit of data (i.e. a logical one or zero) in a complementary manner (e.g., node 113 stores a data bit D and node 115 store the complemented data bit D). Access transistor 116 couples node 113 to a bit line BL, and access transistor 118 couples node 115 to a complementary bit line BL. The gates of access transistors 116 and 118 are connected to a word line WL, which upon being activated, enables data to be written to and/or read from the memory cell 110 via the bit lines BL and BL. A pair of PMOS bit line pre-charge transistors 106 and 108 are connected between a supply voltage VDD and the bit lines BL and BL, respectively, to pre-charge the bit lines for read and/or write operations in response to a read/write pre-charge signal PC_RW.
The compare circuit 120 includes four transistors 122, 124, 126, and 128. Transistors 122 and 124 are connected in series to form a first signal path between a match line ML and ground potential. The transistors 126 and 128 are connected in series to form a second signal path between the match line ML and ground potential. The gates of transistors 122 and 126 are connected to the data bit D and complementary data bit D, respectively, stored in the memory cell 110. The gate of transistor 128 is connected to a compare line CL, while the gate of transistor 124 is connected to a complementary compare line CL. The compare circuit 120 compares the data stored in the memory cell 110 with comparand data provided on compare lines CL and CL, and indicates the match results of CAM cell 100 by selectively discharging the match line ML. Typically, the match line is pre-charged (e.g., to VDD) prior to compare operations. Then, during compare operations, if the data stored in CAM cell 100 matches the comparand data, compare circuit 120 does not turn on and thus the match line ML remains in its pre-charged state to indicate the match condition. Conversely, if there is not a match, compare circuit 120 turns on and discharges the match line ML to ground potential to indicate the mismatch condition.
Existing CAM architectures are increasingly difficult to scale as device geometries continue to become smaller. More specifically, the difficulties of fabricating RAM cells below 45 nanometers limits the scalability of CAM devices that include such memory technologies. For example, referring to FIG. 1, as the die area of the SRAM cell 110 decreases so does the node capacitance between the inverters 112 and 114, which undesirably increases the susceptibility of nodes 113 and 115 to inadvertent logic changes (e.g., caused by single event upsets). As a result, the soft error rate of CAM cell 100 typically increases as device geometry decreases, thereby essential limiting the scalability of such CAM cells. DRAM-based CAM architectures suffer from similar restrictions, due to the amount of die area needed to maintain a given capacitance for storing charge.
Additionally, RAM-based CAM devices are volatile, and therefore must be continually powered to preserve data stored therein. The need for continual power undesirably restricts the application and durability of such RAM-based CAM devices.
Thus, it would be desirable to reduce the size and power consumption of a CAM cell, and to preserve the data stored in the CAM cell in the absence of power.